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Author Topic: Fixed an RV32ec compiler regression, added optional per-subarch RISC-V rtl dirs  (Read 186 times)

MattBradford

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Fixed an RV32ec compiler regression, added optional per-subarch RISC-V rtl dirs
« on: June 27, 2026, 05:40:53 am »
Also added a means of trimming the number of interrupt vectors allocated at compile time so that resource-constrained MCUs can use some of the dormant vector area for actual code.
The per subarch RTL search looks for a specific subarch folder in the RV32-embedded target.  If there isn't one, it reverts to the old flat single architecture folder for the RTL.  So each variant can have parallel RTLs.
The RV32EC subarch had a regression in the register allocator that broke RTL compiling for that target.

Do I need to do anything besides the pull request submittal on GitLab to push it into the main branch?
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ccrause

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Re: Fixed an RV32ec compiler regression, added optional per-subarch RISC-V rtl dirs
« Reply #1 on: June 27, 2026, 12:46:48 pm »
Quote from: MattBradford on June 27, 2026, 05:40:53 am
Do I need to do anything besides the pull request submittal on GitLab to push it into the main branch?

This is basically how it is done.  If you want to you can also post on the fpc-devel mailing list to try and catch the attention of a core developer such as Florian or Jeppe.  Some effort should be going into finalizing the next compiler release, so it may take a while before a core developer reviews this contribution.
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