The table shows 6 macro ops/clock (1/6) for the fastest instructions, so 6 per cycle. Note that "mov reg,reg" (both regs same size) are not emitted, but solved by register rename.
Googles AI says something similar:
It looks like you are asking about the micro-operation (µop) emission, decode, or dispatch throughput of Intel's Golden Cove architecture (used in 12th-14th Gen Core P-Cores). Golden Cove widened the pipeline significantly compared to previous Intel architectures, handling multiple instructions per cycle depending on the stage:
Decode & Emission
- MITE (Legacy Decoders): Can decode up to 6 instructions per cycle (up from 4 in prior architectures like Sunny Cove).
- DSB (µop Cache): Can emit/deliver up to 8 µops per cycle to the µop queue.Back-End Execution (Dispatch & Issue)
- Allocation / Rename: The back-end can dispatch up to 8 instructions per cycle to the rename/allocation buffers.
- Execution Ports: The core features 12 execution ports, allowing it to issue up to 12 µops to the functional units (e.g., ALUs, AGUs, and FPU) simultaneously in a single cycle.Retirement: Can retire up to 12 µops per cycle.
Note that that such peak values are rare. Besides the instructions/cycle limit, for the decoders there is also a byte limit (16 bytes per cycle, but that value is a bit old, maybe increased in very recent CPUs).
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