AARCH64, instruction encoding

[LemonParty]

Hello.
I trying to figure out how encoding of AARCH64 instructions occur. And can't understand how immediate value and register are encoded. I studying instruction movz https://developer.arm.com/documentation/ddi0602/2025-06/Base-Instructions/MOVZ--Move-wide-with-zero-
Does anybody know how it work?

[jamie]

Looks to me like the other Movz I've seen.

Move a smaller type into a larger type and zero out the leftover region of the destination.

So, a 16 bit memory type can be moved into a 32/64 bit register with the remainder cleared?

Just my guess really..

Jamie

[Khrys]

Here's an example for moving  0xABCD'0000'0000'0000  into  x0:

movz x0, #0xABCD, lsl #48

1 10100101 11 1010101111001101 00000
│        │  │                │     └─ Rd (aka Xd because sf = 1); 0 → x0
│        │  │                └─────── imm16; 0xABCD
│        │  └──────────────────────── hw;    3      → shift left by 48 bits
│        └─────────────────────────── opc;   0xA5   → movz opcode
└──────────────────────────────────── sf;    1      → 64-bit destination

[LemonParty]

Thank you, Khrys. This helped.

[LemonParty]

If anybody else interesting in this topic I found a site with a good documentation:
https://finkmartin.com/aarch64/index.html

[Khrys]

If anybody else interesting in this topic I found a site with a good documentation:
https://finkmartin.com/aarch64/index.html

Thanks for sharing this!    I'll add a bookmark and place it next to Félix Cloutier's x86 reference.
Love this kind of static site that loads instantly and does only one thing, but does so extremely well.