Usually this is assembler agnostic:
DB 0x90, 0x90, 0x90 // Three Intel NOP instructions in a row
You should be able to use the same for AARCH64. As long as you know the instruction byte order, that is.
You obviously did not know about the db instruction/directive..
It works, the code example is for intel though.
Fully supported for AARCH64 instructions in byte notation.