What is more (memory) efficient

[ALLIGATOR]

What makes you believe that with the proposed code you are analyzing the performance of the processor cache?

Different step size for accessing data in memory

[DragoRosso]

Yes, that was a good article to understand how the cache works.

But, you don't know how the compiler optimize or simply "translate" your code. May be in assembler view should be the better way to analyze the fact. And you are sure about your interpretation of memory cache alghoritm ? I don't think that someone know it to determine exactly the function in this way (multi-level N-way set-associative caches questions).

Other important things is that you are running a simple "routine" in a user level, with lower priority than the other "routines" of your system like drivers or others software that run at kernel mode or at other priority level.

So you are "measure" the performance of your system, not cache processor, 'cause your routine wil be interrupt a lot of time, and you don't know if your code is running in more than one thread (also inside the same core).

Other things are about all new "innovation" with new architecture like hybrid core, ITD (Intel thread director) and others ...

[ALLIGATOR]

But, you don't know how the compiler optimize or simply "translate" your code. May be in assembler view should be the better way to analyze the fact.

I'm well aware of how this code optimized the compiler - since I'm looking at it, you're hopefully aware of this feature?

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Other important things is that you are running a simple "routine" in a user level, with lower priority than the other "routines" of your system like drivers or others software that run at kernel mode or at other priority level.

So you are "measure" the performance of your system, not cache processor, 'cause your routine wil be interrupt a lot of time, and you don't know if your code is running in more than one thread (also inside the same core).

Well, come on, because you yourself said that the article is good - so read it ) it says in black and white how you can determine the size of caches and their latency, at a fairly accurate level being in the third ring under the operating system. Again, it is not a problem for those who know what they are doing. For those who do not understand - yes, it may seem like magic!

Yes, that was a good article to understand how the cache works.

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Other things are about all new "innovation" with new architecture like hybrid core, ITD (Intel thread director) and others ...

The technologies you have listed are easily configurable from the user mode, and even a simple setting of the correspondence to the processor core will level their influence up to 0

[ALLIGATOR]

What makes you believe that with the proposed code you are analyzing the performance of the processor cache?

In turn, then I have to ask you - what makes you doubt that my code is not related to cache access performance analysis?

[Mr.Madguy]

If memory isn't issue, then it's better to rely on default alignment, as it's better for performance.

[440bx]

If memory isn't issue, then it's better to rely on default alignment, as it's better for performance.

Actually, the measurements shown in this thread give a strong impression of the opposite being true.

The default is unpacked, which means aligned.  The measurements shown in this thread show that accessing fields in a packed structure is faster.

Honestly, in spite of the results that have been posted in this thread, I still believe that aligned data is accessed faster.  I suspect/guess that the results seen here are more likely to be a result of the compiler's ability to optimize some cases better than others, not really due to differences in access speed due to alignment.  That said, I'd be really hard pressed to prove this belief.

[DragoRosso]

What makes you believe that with the proposed code you are analyzing the performance of the processor cache?

In turn, then I have to ask you - what makes you doubt that my code is not related to cache access performance analysis?

I don't have any doubts, I'm certain that your code is not related to cache (EDIT: TO MEASURE THE PERFORMANCE OF), I hoped that you explain why you think so, but you only explain about facts that are not in your code.

I don't want to continue useless polemics. So for me the discussion ends here.
Sorry if I questioned what you proposed.