What is the current status of Risc-V Target?

[MiR]

I just received a few cheap Risc-V boards from China:

https://www.seeedstudio.com/Sipeed-Longan-Nano-RISC-V-GD32VF103CBT6-Development-Board-p-4205.html

https://www.seeedstudio.com/Sipeed-Maixduino-for-RISC-V-AI-IoT-p-4046.html

does anybody know what the status of the Risc-V Target is?

It looks like on the extra branch for this there was no activity for nearly a year. Is the target already useable?

MiR

[marcov]

The riscv branch was merged into trunk on sept 28th, 2018. So that branch is now stale.

I don't know what the exact status of the risc port is.

[MiR]

Good to know, I just followed the documentation in the wiki and that still points to the extra branch(es)

[Laksen]

I would consider the RISC-V 64 bit target in trunk basically working. It's not tested nightly due to lack of hardware.

RISC-V 32 bit is not tested and cleaned up, but might work. Once hardware, like the Sipeed stuff, starts becoming available it will get worked on

[MiR]

Sounds good, I will give the 64bits version a try....

MiR

[_Bernd]

I am testing RISC-V 32 embedded with PicoRV32 in a FPGA. Basic stuff seems to work. Nice :-)

Regards, Bernd.

[PascalDragon]

I am testing RISC-V 32 embedded with PicoRV32 in a FPGA. Basic stuff seems to work. Nice :-)

If you discover problems, don't hesitate to report them, cause while I got riscv64-linux working, riscv32-linux aborts with a segmentation fault when initializing the standard input/output, so there is probably still some problem with code generation (if I had to guess I'd say parameter passing with var parameters as it fails in Assign when accesing the file record).

[MiR]

I also started work, implemented controller units for the logan nano and the hifive rev b board. i have yet to understand how interrupts work on those chips.....

[_Bernd]

I wonder, if someone was successful with the GD32VF103 controller.

I had to make two small modifications to the riscv32 rtl startup code, to get programs run on a GD32VF103 controller.

The first entry in the interrupt vector table did not contain a jump to the startup code location.
Starting a program via the internal boot loader then worked, but running a program at power on reset failed.

At power on reset, the controller starts executing at address 0x00000000, but the flash start address is 0x08000000 (both address ranges point to the same physical memory) for which the program is correctly linked. The startup code now checks, if the program counter is below 0x08000000 and switches to 0x08nnnnnn if needed.

Regards, Bernd.

[_Bernd]

If you discover problems, don't hesitate to report them, cause while I got riscv64-linux working, riscv32-linux aborts with a segmentation fault when initializing the standard input/output, so there is probably still some problem with code generation (if I had to guess I'd say parameter passing with var parameters as it fails in Assign when accesing the file record).

The following program fails on the GD32VF103 controller.

Code: Pascal  [Select][+][-]

1. program test;
2. {$mode objfpc}{$H-}
3. var
4.    s: ShortString;
5.  
6. procedure TestShortString(sIn: ShortString);
7. var
8.    b: Byte;
9. begin
10.    b:= Ord(sIn[1]);  // b = 'L' = 76
11.    if b <> 76 then begin
12.       { executes here! }
13.       repeat
14.       until FALSE;
15.    end;
16.    asm
17.       ebreak;
18.    end;
19. end;
20.  
21. begin
22.    s:= 'Laberhannes';
23.    TestShortString(s);
24. end.
25.  

Something seems to go wrong with the local copy of the shortstring  variable sIn. If sIn is declared as var, then the program runs correct.

Regards, Bernd.

[MiR]

Espressif will base a new esp32 version on riscv32:

https://hackaday.com/2020/11/22/espressif-leaks-esp32-c3-a-wifi-soc-thats-risc-v-and-is-esp8266-pin-compatible/

[MarkMLl]

I was just wondering the other evening how much work would be involved in modifying the Escape DLX simulator that Jonas et al. contributed a few years ago for RISC-V. https://github.com/jmaebe/ESCAPE

MarkMLl

[_Bernd]

Hello,

I am currently porting a project (about 10000 lines of code) from AVR to STM32F103/ARM Cortex M3 and simultaneously to GD32VF103/RISC-V/RV32IMAC and this goes pretty well. In my opinion, the state of the RISC-V compiler is surprisingly good. Hut ab ;-)

There is a minor issue concerning interrupts (https://bugs.freepascal.org/view.php?id=38348). When the non vectored interrupt feature of the GD32VF103 interrupt controller is sufficient, then Pascal interrupt procedures are working. In vectored mode, one could write inline assembler interrupt routines with the nostackframe attribute.

As far as I can see at the moment, the execution speed of the GD32VF103 is faster than the STM32F103.  I think the main reason for this is, that the STM32F103 needs two wait states, when the program runs from Flash. The code size is roughly twice as large for the RISC-V controller.

Regards, Bernd.

[jma_sp]

Hello,
How can i start learning to use FreePascal for RISC-V?
What are the steps to install RISC-V RTL, under what OS, How?
Any advise?
I have been see that fpcupdeluxe have an option to generate something...

[kupferstecher]

@jma_sp, which device do you want to use?

Before, I did some tests on the CH32V307, basic functionality worked. Later I ported a project to the CH32V103, basic tests also worked, but the larger project crashed repeatedly shortly after startup when powering some periphery, could be a hardware issue though. I didn't investigate further due to lack of time.

The compiler I generate with a short batch file. Works quite well. If you are interested, I can share it.