Cortex-M4 'startup' code in the Embedded RTL

[AndyPreston]

I'm playing around with the idea of a custom RTL for my STM32F401CC board and, inevitably, I've come across the startup code in ./rtl/embedded/arm/cortexm4f_start.inc

First we see a routine that fills from L_data to L_edata with a copy of whatever comes at L_etext

The there's another routine that fills from L_bss_start to L_bss_end with zero / null / nil.

Then we branch to PASCALMAIN - which is the only part that makes complete sense to me.

I understand what this code is doing and like to think I know my way around an ELF file.
But I don't understand WHY these two pieces of code exist. and it's the "why" I'm really looking for.

Clearing out RAM makes complete sense but I'd like to know why it's strictly necessary.

But copying data from etext into data completely mystifies me... what is this data that comes after the end of the text section?

If there's anyone out there who's au-fait with the embedded RTL (and probably some compiler internals)... can you help end my confusion?

Thanks.

[marcov]

1. zeroing memory :   more determinism and refcounted types rely on it.
2. copying flash to memory : usually speed. Flash runs slower than ram(*)

(*) Sometimes the flash bus is wider though so when running linear (non branching code) an effective higher speed is achieved, with heavier penalties on branching.

[AndyPreston]

1. zeroing memory :   more determinism and refcounted types rely on it.

makes sense, thanks

2. copying flash to memory : usually speed. Flash runs slower than ram

So is the data section in RAM?.. I'd assumed only bss was in RAM
And if the "stuff" from etext onward is the statically initialised data... what section is it in? Is it still in text even though it's after etext?