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Author Topic: What is the current status of Risc-V Target?  (Read 1384 times)

MiR

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What is the current status of Risc-V Target?
« on: November 02, 2019, 03:09:34 pm »
I just received a few cheap Risc-V boards from China:

https://www.seeedstudio.com/Sipeed-Longan-Nano-RISC-V-GD32VF103CBT6-Development-Board-p-4205.html

https://www.seeedstudio.com/Sipeed-Maixduino-for-RISC-V-AI-IoT-p-4046.html

does anybody know what the status of the Risc-V Target is?

It looks like on the extra branch for this there was no activity for nearly a year. Is the target already useable?

MiR

marcov

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Re: What is the current status of Risc-V Target?
« Reply #1 on: November 02, 2019, 03:16:35 pm »
The riscv branch was merged into trunk on sept 28th, 2018. So that branch is now stale.

I don't know what the exact status of the risc port is.

MiR

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Re: What is the current status of Risc-V Target?
« Reply #2 on: November 02, 2019, 03:19:43 pm »
Good to know, I just followed the documentation in the wiki and that still points to the extra branch(es)

Laksen

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Re: What is the current status of Risc-V Target?
« Reply #3 on: November 02, 2019, 03:21:55 pm »
I would consider the RISC-V 64 bit target in trunk basically working. It's not tested nightly due to lack of hardware.

RISC-V 32 bit is not tested and cleaned up, but might work. Once hardware, like the Sipeed stuff, starts becoming available it will get worked on :)

MiR

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Re: What is the current status of Risc-V Target?
« Reply #4 on: November 02, 2019, 03:24:06 pm »
Sounds good, I will give the 64bits version a try....

MiR

_Bernd

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Re: What is the current status of Risc-V Target?
« Reply #5 on: December 28, 2019, 01:55:33 am »
I am testing RISC-V 32 embedded with PicoRV32 in a FPGA. Basic stuff seems to work. Nice :-)

Regards, Bernd.

PascalDragon

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Re: What is the current status of Risc-V Target?
« Reply #6 on: December 28, 2019, 09:19:07 am »
I am testing RISC-V 32 embedded with PicoRV32 in a FPGA. Basic stuff seems to work. Nice :-)
If you discover problems, don't hesitate to report them, cause while I got riscv64-linux working, riscv32-linux aborts with a segmentation fault when initializing the standard input/output, so there is probably still some problem with code generation (if I had to guess I'd say parameter passing with var parameters as it fails in Assign when accesing the file record).

MiR

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Re: What is the current status of Risc-V Target?
« Reply #7 on: December 28, 2019, 09:29:18 am »
I also started work, implemented controller units for the logan nano and the hifive rev b board. i have yet to understand how interrupts work on those chips.....

_Bernd

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Re: What is the current status of Risc-V Target?
« Reply #8 on: August 09, 2020, 10:51:35 pm »
I wonder, if someone was successful with the GD32VF103 controller.

I had to make two small modifications to the riscv32 rtl startup code, to get programs run on a GD32VF103 controller.

The first entry in the interrupt vector table did not contain a jump to the startup code location.
Starting a program via the internal boot loader then worked, but running a program at power on reset failed.

At power on reset, the controller starts executing at address 0x00000000, but the flash start address is 0x08000000 (both address ranges point to the same physical memory) for which the program is correctly linked. The startup code now checks, if the program counter is below 0x08000000 and switches to 0x08nnnnnn if needed.

Regards, Bernd.

_Bernd

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Re: What is the current status of Risc-V Target?
« Reply #9 on: August 16, 2020, 12:25:45 am »
If you discover problems, don't hesitate to report them, cause while I got riscv64-linux working, riscv32-linux aborts with a segmentation fault when initializing the standard input/output, so there is probably still some problem with code generation (if I had to guess I'd say parameter passing with var parameters as it fails in Assign when accesing the file record).

The following program fails on the GD32VF103 controller.

Code: Pascal  [Select][+][-]
  1. program test;
  2. {$mode objfpc}{$H-}
  3. var
  4.    s: ShortString;
  5.  
  6. procedure TestShortString(sIn: ShortString);
  7. var
  8.    b: Byte;
  9. begin
  10.    b:= Ord(sIn[1]);  // b = 'L' = 76
  11.    if b <> 76 then begin
  12.       { executes here! }
  13.       repeat
  14.       until FALSE;
  15.    end;
  16.    asm
  17.       ebreak;
  18.    end;
  19. end;
  20.  
  21. begin
  22.    s:= 'Laberhannes';
  23.    TestShortString(s);
  24. end.
  25.  

Something seems to go wrong with the local copy of the shortstring  variable sIn. If sIn is declared as var, then the program runs correct.

Regards, Bernd.

 

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