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What is the current status of Risc-V Target?
MiR:
Espressif will base a new esp32 version on riscv32:
https://hackaday.com/2020/11/22/espressif-leaks-esp32-c3-a-wifi-soc-thats-risc-v-and-is-esp8266-pin-compatible/
MarkMLl:
I was just wondering the other evening how much work would be involved in modifying the Escape DLX simulator that Jonas et al. contributed a few years ago for RISC-V. https://github.com/jmaebe/ESCAPE
MarkMLl
_Bernd:
Hello,
I am currently porting a project (about 10000 lines of code) from AVR to STM32F103/ARM Cortex M3 and simultaneously to GD32VF103/RISC-V/RV32IMAC and this goes pretty well. In my opinion, the state of the RISC-V compiler is surprisingly good. Hut ab ;-)
There is a minor issue concerning interrupts (https://bugs.freepascal.org/view.php?id=38348). When the non vectored interrupt feature of the GD32VF103 interrupt controller is sufficient, then Pascal interrupt procedures are working. In vectored mode, one could write inline assembler interrupt routines with the nostackframe attribute.
As far as I can see at the moment, the execution speed of the GD32VF103 is faster than the STM32F103. I think the main reason for this is, that the STM32F103 needs two wait states, when the program runs from Flash. The code size is roughly twice as large for the RISC-V controller.
Regards, Bernd.
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