FPC Feature Request - Enhanced Memory Manager

[MathMan]

Hi all,

I am currently running FPC 2.6.4 but have so far not looked into the looming FPC 3.x.x - so my request may already be addressed.

I understand that there is a way to integrate self developed memory Managers but there is one simple thing that might enhance usability if integrated into the core RTL.

What I would like to be able is to control the alignment of memory allocated on the heap via a control - e.g. {$HEAP_ALIGN xx} where xx is a power of 2. I see this in terms of software optimization as this way I could align heap memory to processor cache line sizes (and other stuff).

What are your thoughts - is this reasonable? And if so how to proceed?

Kind regards,
MathMan

[Leledumbo]

Adding compiler directives require you to modify the compiler. You can of course use the macro system to supply that value instead.

[marcov]

The memory manager is a library (rtl/inc/heap*),  and to modify it that way you wouldn't need to modify the compiler.

Extract those files to an unit, modify it to force 16-byte alignment, load it as first unit in your program, and it should work.

The heapmgr is not simple though.

[Laksen]

The current memory manager aligns blocks at 16 bytes and 32 bytes for 64 bit targets already.

Not sure which instructions would gain from anything above that?

[MathMan]

The memory manager is a library (rtl/inc/heap*),  and to modify it that way you wouldn't need to modify the compiler.

Extract those files to an unit, modify it to force 16-byte alignment, load it as first unit in your program, and it should work.

The heapmgr is not simple though.

As said above I am willing to take that route but first wanted to explore common view on making the alignment value accessible in general.

Before I start working on this - is there somebody around who did this already and could hint me to the places in the sources that I would need to change? I fully agree that the heapmgr is not simple, and before I spend hours in futile work I'll gladly take any hints from experts.

[marcov]

The current memory manager aligns blocks at 16 bytes and 32 bytes for 64 bit targets already.

Not sure which instructions would gain from anything above that?

AVX512 in Skylake this year? 

[MathMan]

The current memory manager aligns blocks at 16 bytes and 32 bytes for 64 bit targets already.

Not sure which instructions would gain from anything above that?

It's not about making a single instruction fast but mainly speeding up routines in general by working on data chunks which are in line with the cache structure. E.g. on the low level one can move data from memory into the processor in a very fast way by utilizing certain SSE instructions which require that 64 bytes are read in sequence - MOVDQA instruction. On higher levels one can arrange loops working with data in a more efficient way if the data is aligned to cache line sizes. Finally it should be possible to minimize cache trashing effects.

[hnb]

Before I start working on this - is there somebody around who did this already and could hint me to the places in the sources that I would need to change? I fully agree that the heapmgr is not simple, and before I spend hours in futile work I'll gladly take any hints from experts.

Try to ask in mailing list ( fpc-devel ).

http://www.freepascal.org/maillist.var