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Author Topic: Lazarus and Reconfigurable virtual instrumentation with FPGA  (Read 8798 times)

M.A.R.C.

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Lazarus and Reconfigurable virtual instrumentation with FPGA
« on: January 16, 2018, 07:49:33 am »
We programmed several instruments GUI using mainly Lazarus.  We think that is a good time to make the Lazarus programming more visible and We take the opportunity to participate in an Intel contest.

(http://www.innovatefpga.com/attachment/member/2017/AS033-7CF76E7B53291F71/Main.gif)

Review our project, if you like it please vote for us and share it: Do you want to get an oscilloscope, waveform generator, IV Curve Tracer and Data Logger? Don't forget to register, login and vote for us in the Intel InnovateFPGA contest: http://www.innovatefpga.com/cgi-bin/innovate/teams.pl?Id=AS033

Every week during the first round and regional semi-final voting periods, two community members will be chosen at random to receive a free Terasic DE10-Nano kit.

Thank you!

Miguel
« Last Edit: January 16, 2018, 07:53:02 am by mrisco »

madref

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Re: Lazarus and Reconfigurable virtual instrumentation with FPGA
« Reply #1 on: January 16, 2018, 09:09:10 am »
Is this allowed on this forum???
You treat a disease, you win, you lose.
You treat a person and I guarantee you, you win, no matter the outcome.

Lazarus 3.99 (rev main_3_99-649-ge13451a5ab) FPC 3.3.1 x86_64-darwin-cocoa
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avra

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Re: Lazarus and Reconfigurable virtual instrumentation with FPGA
« Reply #2 on: January 16, 2018, 09:10:56 am »
Very nice work!  :)  8-) :)

Too bad ADC is only 500ksps  :'(
ct2laz - Conversion between Lazarus and CodeTyphon
bithelpers - Bit manipulation for standard types
pasettimino - Siemens S7 PLC lib

taazz

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Re: Lazarus and Reconfigurable virtual instrumentation with FPGA
« Reply #3 on: January 16, 2018, 09:52:57 am »
Very nice work!  :) 8-) :)

Too bad ADC is only 500ksps  :'(
1) Has the frequency measuring unit changed from Hz to sps for some reason?
2) what is an acceptable average frequency you are looking for? Isn't 2*10^-6 fast enough? that's 2μs. What do you need to measure?
Good judgement is the result of experience … Experience is the result of bad judgement.

OS : Windows 7 64 bit
Laz: Lazarus 1.4.4 FPC 2.6.4 i386-win32-win32/win64

taazz

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Re: Lazarus and Reconfigurable virtual instrumentation with FPGA
« Reply #4 on: January 16, 2018, 09:54:23 am »
Is this allowed on this forum???
I hope so the wider the target market is the better for all of us.
Good judgement is the result of experience … Experience is the result of bad judgement.

OS : Windows 7 64 bit
Laz: Lazarus 1.4.4 FPC 2.6.4 i386-win32-win32/win64

avra

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Re: Lazarus and Reconfigurable virtual instrumentation with FPGA
« Reply #5 on: January 16, 2018, 11:03:58 am »
Very nice work!  :) 8-) :)

Too bad ADC is only 500ksps  :'(
1) Has the frequency measuring unit changed from Hz to sps for some reason?
SPS stands for samples per second. You need at least 5-6 samples for minimal representation of digitized analogue signal (ideally 10 or more). Therefore such ADC can help you see up to 80kHz analogue signal forms. I have Usbee DX (https://www.usbee.com/dx.html) which has 24Msps, but it is good only for analogue signals up to 6MHz (and that's optimistic value). When you use more channels, sampling is serialized so frequency is divided by number of sampling channels.

2) what is an acceptable average frequency you are looking for? Isn't 2*10^-6 fast enough? that's 2μs. What do you need to measure?
Well, to get a descent representation of even an ancient TV composite analogue signal, you need to sample it with at least 12Msps. Otherwise some important info might be missed. People who have generated composite video or VGA signal, or grabbed an analogue camera signal in pure software will know the difference.
https://en.wikipedia.org/wiki/Sampling_(signal_processing)#Video_sampling
ct2laz - Conversion between Lazarus and CodeTyphon
bithelpers - Bit manipulation for standard types
pasettimino - Siemens S7 PLC lib

M.A.R.C.

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Re: Lazarus and Reconfigurable virtual instrumentation with FPGA
« Reply #6 on: January 16, 2018, 04:01:01 pm »
Thank you for all your replies, the limit of 500ksps is only for the ADC included in the mainboard (that is enough for data logger and maybe for the IV curve tracer). The real limits depends mainly of the additional hardware that you add in the shape of a daughter board. Because the DE10-Nano supports the Arduino Uno shields is possible to use several third-party boards, some of them with very more capable ADC and DAC. The great about of this project is that you can use the software and firmware developed to create, customize and extend your instruments.
« Last Edit: January 16, 2018, 04:02:40 pm by mrisco »

taazz

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Re: Lazarus and Reconfigurable virtual instrumentation with FPGA
« Reply #7 on: January 16, 2018, 09:44:43 pm »
Very nice work!  :) 8-) :)

Too bad ADC is only 500ksps  :'(
1) Has the frequency measuring unit changed from Hz to sps for some reason?
SPS stands for samples per second. You need at least 5-6 samples for minimal representation of digitized analogue signal (ideally 10 or more). Therefore such ADC can help you see up to 80kHz analogue signal forms. I have Usbee DX (https://www.usbee.com/dx.html) which has 24Msps, but it is good only for analogue signals up to 6MHz (and that's optimistic value). When you use more channels, sampling is serialized so frequency is divided by number of sampling channels.
Does that mean that you average(max/min etc depending on the use case) the results of 5~6 samples to a single one? that makes some sense (read error correction and all).
2) what is an acceptable average frequency you are looking for? Isn't 2*10^-6 fast enough? that's 2μs. What do you need to measure?
Well, to get a descent representation of even an ancient TV composite analogue signal, you need to sample it with at least 12Msps. Otherwise some important info might be missed. People who have generated composite video or VGA signal, or grabbed an analogue camera signal in pure software will know the difference.
https://en.wikipedia.org/wiki/Sampling_(signal_processing)#Video_sampling
Oh yeah there are signals in the MHz and GHz range too that would make things a bit restricted didn't think about that.
Good judgement is the result of experience … Experience is the result of bad judgement.

OS : Windows 7 64 bit
Laz: Lazarus 1.4.4 FPC 2.6.4 i386-win32-win32/win64

JD

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Re: Lazarus and Reconfigurable virtual instrumentation with FPGA
« Reply #8 on: January 17, 2018, 03:21:52 am »
Is this allowed on this forum???
I hope so the wider the target market is the better for all of us.

I fully agree.  :D
Windows - Lazarus 2.1/FPC 3.2 (built using fpcupdeluxe),
Linux Mint - Lazarus 2.1/FPC 3.2 (built using fpcupdeluxe)

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avra

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Re: Lazarus and Reconfigurable virtual instrumentation with FPGA
« Reply #9 on: January 17, 2018, 08:52:39 am »
Does that mean that you average(max/min etc depending on the use case) the results of 5~6 samples to a single one? that makes some sense (read error correction and all).
No. Imagine that you are sampling a simple sine signal of 10Hz as shown on the attached image. If you are doing it with 1ksps, you can without any doubt recognize the sine wave. Even with 100sps you still see a sine wave. With 50sps it is difficult but your brain helps you guess it is still sine wave if it knows what to expect, but if it doesn't then it might also make you think it is a sawtooth (crosses are actual sampled values). With 30sps and less it is almost impossible to even guess the wave form. If you are lucky you will sample at the moment when peaks are reached so you see square wave, but if you are not lucky then you will sample at moments when signal passes zero so you will get straight line instead of signal. So, for sampling analogue signals minimum is 5-6 times sampling rate of the signal max frequency, and ideally 10 times or more. Remember that real world signals are more complex then single sine wave.

Some random educational info on the topic:
https://community.plm.automation.siemens.com/t5/Testing-Knowledge-Base/Digital-Signal-Processing-Sampling-Rates-Bandwidth-Spectral/ta-p/402991
« Last Edit: January 17, 2018, 08:56:19 am by avra »
ct2laz - Conversion between Lazarus and CodeTyphon
bithelpers - Bit manipulation for standard types
pasettimino - Siemens S7 PLC lib

avra

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Re: Lazarus and Reconfigurable virtual instrumentation with FPGA
« Reply #10 on: January 17, 2018, 09:25:21 am »
The great about of this project is that you can use the software and firmware developed to create, customize and extend your instruments.
That is a true value of your project for the rest of us. For you it was also an invaluable learning experience to write everything from scratch and bring all peaces together. For me, the interesting part is communication between internal FPGA and on board Lazarus code. I see communication block on the images but nothing more. I can only guess that serial link is internal, but it could also be externaly wired.  I can also only guess that ethernet and bluetooth are going through Lazarus code, and not directly accessed from VHDL code. I did not study the board so I am in the dark here. Could you bring a little light on this with just a few sentences, please? Did I understand well that sources will be available only if you win the competition?
ct2laz - Conversion between Lazarus and CodeTyphon
bithelpers - Bit manipulation for standard types
pasettimino - Siemens S7 PLC lib

taazz

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Re: Lazarus and Reconfigurable virtual instrumentation with FPGA
« Reply #11 on: January 17, 2018, 09:57:21 am »
Does that mean that you average(max/min etc depending on the use case) the results of 5~6 samples to a single one? that makes some sense (read error correction and all).
No. Imagine that you are sampling a simple sine signal of 10Hz as shown on the attached image. If you are doing it with 1ksps, you can without any doubt recognize the sine wave. Even with 100sps you still see a sine wave. With 50sps it is difficult but your brain helps you guess it is still sine wave if it knows what to expect, but if it doesn't then it might also make you think it is a sawtooth (crosses are actual sampled values). With 30sps and less it is almost impossible to even guess the wave form. If you are lucky you will sample at the moment when peaks are reached so you see square wave, but if you are not lucky then you will sample at moments when signal passes zero so you will get straight line instead of signal. So, for sampling analogue signals minimum is 5-6 times sampling rate of the signal max frequency, and ideally 10 times or more. Remember that real world signals are more complex then single sine wave.

Some random educational info on the topic:
https://community.plm.automation.siemens.com/t5/Testing-Knowledge-Base/Digital-Signal-Processing-Sampling-Rates-Bandwidth-Spectral/ta-p/402991
oh you mean samples per cycle. I now see the need to distinguish between sps and Hz.
Good judgement is the result of experience … Experience is the result of bad judgement.

OS : Windows 7 64 bit
Laz: Lazarus 1.4.4 FPC 2.6.4 i386-win32-win32/win64

M.A.R.C.

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Re: Lazarus and Reconfigurable virtual instrumentation with FPGA
« Reply #12 on: January 17, 2018, 02:27:30 pm »
...For me, the interesting part is communication between internal FPGA and on board Lazarus code. I see communication block on the images but nothing more. I can only guess that serial link is internal, but it could also be externaly wired.  I can also only guess that ethernet and bluetooth are going through Lazarus code, and not directly accessed from VHDL code...
We have two web page (http://ue.accesus.com) where some of our projects are published, one of them is a thesis and it is already published. The main differences between the competition project and the listed in the web are the DE10-Nano board, the fact that we are going to put some of the GUI directly in the HPS, and we are going to put order and unify the base of the instruments to be more useful to the community.

At the end of the competition, the sources will be published by Intel on Github repository.
« Last Edit: January 18, 2018, 04:43:33 am by mrisco »

M.A.R.C.

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Re: Lazarus and Reconfigurable virtual instrumentation with FPGA
« Reply #13 on: January 21, 2018, 02:34:43 am »
I want to say thanks to all members who put their quality comments on the contest page of our project! You make us better!

M.A.R.C.

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Re: Lazarus and Reconfigurable virtual instrumentation with FPGA
« Reply #14 on: January 27, 2018, 06:40:36 pm »
Only three days to end the competition. We need you, if you like our project please vote for us:
http://www.innovatefpga.com/cgi-bin/innovate/teams.pl?Id=AS033

Thanks

 

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